Design Automation
Domain-specific high-level synthesis and automated architecture generation.
Biography
I am a Professor with the School of Computer Science and Technology at Huazhong University of Science and Technology (HUST). My work explores efficient computer systems through specialized hardware, software–hardware co-design, and automation.
Before joining HUST, I was a Research Assistant Professor at the National University of Singapore, where I collaborated with Prof. Bingsheng He and Prof. Weng-Fai Wong. Earlier, I was a Senior Research Scientist at the Advanced Digital Sciences Center, a UIUC-affiliated research center in Singapore.
Research Areas
Domain-Specific Accelerators
FPGA-enabled domain-specific architectures for data-intensive and emerging applications.
Hardware–Software Co-design
Efficient ML and graph accelerators, heterogeneous systems, and on-device AI.
Recent News
All publications →- PaperHiCAM: Accelerating Parallel Triangle Counting via Bit-Efficient Content-Addressable Memory on FPGA accepted by MICRO 2026.
- PaperRidgeBridge: Random Access Optimized Interconnect Architecture for Scalable Graph Random Walks accepted by MICRO 2026.
- PaperPIMCQG: Co-Designing Billion-Scale Graph-Based Approximate Nearest Neighbor Search for Processing-in-Memory accepted by SC 2026.
- PaperApproaching Shannon Bound with Lossless LLM Weight Compression accepted by ISCA 2026.
- PaperXtraMAC, an efficient mixed-precision LLM inference architecture, accepted by ISCA 2026.
- TalkInvited talk “Revisiting CAM on FPGAs” at the NUS–HUST International Workshop.
Selected Talks
- Revisiting CAM on FPGAsNUS–HUST International Workshop · Singapore · 2025
- From Applications to Efficient Architectures on FPGAsCCF ESTC · Shenzhen · 2024
- Parallel Graph Processing on FPGAsNational University of Defense Technology · 2024